Nanowires in Nanoelectronics
David K. Ferry
For almost four decades, progress in microchips has followed Moore’s (1) famous dictum that the transistor density would double roughly every 18 months. This steady progress has brought us to the point today where leading-edge chips have transistors whose critical dimension is only about 100 atoms long. Clearly, this evolution cannot continue down this same path much longer. Recognition of the impending “end of the road” has led many to seek an alternative to the ubiquitous silicon transistor, hoping thereby to revolutionize the industry that has fueled the massive information revolution since World War II (2, 3). Among the promising candidates are nanowires and transistors made from them (4–7). These nanowires have been grown as carbon nanotubes or from silicon, as well as a variety of other semiconductors.
Going vertical. A schematic, conceptual view of the introduction of vertical nanowires on a microchip. The bottom layer is a chip layout drawing; the various colors represent interconnection levels on the chip. The nanowires can reach from the chip level to higher-lying interconnects or they can reach between various metal layers.
As with most new technologies, there are remarkable expectations for the usefulness of these nanowires. In reality, they are not likely to replace the silicon transistor, but they may well provide the paradigm shift that will extend Moore’s “law.” To understand how this paradigm shift must occur, we need to understand the driving force for Moore’s Law. It is a trend that does not derive from physical science but from economics. Transistors are laid out on the microchip in a planar fashion, much like houses in a modern southwestern city. According to Intel, the latest 45-nm microprocessor (with a gate length—the critical dimension in the direction of current flow—of ~22 nm) has about 410 million transistors in 107 mm2 , or each transistor occupies a square of silicon real estate that is roughly 500 nm on a side. Originally, Moore’s Law was driven by three factors: (i) reducing the transistor size (and therefore the square of silicon upon which it sits), (ii) increasing the size of the microchip itself, and (iii) circuit cleverness (by which the number of transistors needed to perform a function could be reduced with consequent savings in silicon real estate). As the number of transistors increased, the number of functional units in each chip could be increased, thus increasing the computing power per chip. Because the basic cost of manufacturing the microchip has not dramatically increased over these four decades, the cost per functional unit, and the cost of computing power, has gone down exponentially. It is this economic argument, the cost of silicon real estate, that drives Moore’s Law. For the past decade, however, the size of the microchip has remained roughly constant, so that factors (i) and (iii) have become more important. Today, as pointed out above, we are approaching the atomic limit on critical size. We are left, therefore, with the conclusion that it is factor (iii) that will have to provide the continuity to Moore’s Law. What does this say about the role of nanowires? Although transistors have very short gate lengths (the critical dimensions mentioned above), they have much larger widths in order to provide the current necessary to make the circuits work. If we are to replace the current planar transistor with nanowires, we will have to use a great many such devices in parallel to provide this current. But, we must satisfy the above economic driving forces, and effectively use the overall silicon real estate. This leads to a geometric argument that says that nanowires in the plane will not effectively compete with novel transistors such as the “fin” field effect transistor, or “finFET,” Basically, the finFET is a vertically oriented Si “fin” in which transistor structures can be placed on both sides (8, 9), and even on the top (10), of this fin. A properly configured finFET more effectively uses silicon real estate. Consequently, there does not seem to be much of a role for nanowires laid horizontally on the Si surface (11, 12). However, nanowires can be grown vertically, and this growth can be initiated on a wide variety of substrates (4). As mentioned, currently the transistors are placed in a planar array, but they are overlaid with a great many metal lines, with nine or more levels of metal (worse than any freeway interchange). These metal lines provide power, clock signals to synchronize the switching of the transistors, and various interconnections between the different functional blocks of the chip. Connections from these metal lines to the transistors are made by downwardly reaching metal fingers called “vias.” When we can no longer reduce the transistor size, we enhance the use of Si real estate by moving vertically. Our third Moore’s Law factor—cleverness—can be increased by replacing some of these vias with vertical nanowire transistors (13) (see the figure). These vertical transistors can reach from the silicon to a metal wire or even between different levels of metal wire. Moreover, we can begin to think about creating reconfigurable architectures in which the connections between different functional blocks are changed by switching just a few of these vertical transistors. Thus, we begin to create real three-dimensional architectures in a different manner from the traditional approach of stacking chips (14). If we are to use these vertical transistors for more effective architectures, then we have to change how we go about microchip design. Today, this chip design is done with automated transistor layout programs that optimize the planar design placing of the various functional blocks and minimize the necessary interconnections (in the metal layers). To change to reconfigurable architectures, we need switchable interconnections based on vertical transistors, and device physicists will have to work with circuit designers to achieve this. These new opportunities for nanowires to extend Moore’s Law may well force this paradigm shift.
References
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